题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

reg [3:0] G,P,c,s;

always@(*) 
	begin
		G[0] = A_in[0] & B_in[0]; 
		P[0] = A_in[0] ^ B_in[0]; 
		c[0]= G[0] || (P[0] & C_1);
		s[0] = P[0] ^ C_1;

		G[1] = A_in[1] & B_in[1]; 
		P[1] = A_in[1] ^ B_in[1]; 
		c[1]= G[1] || (P[1] & c[0]);
		s[1] = P[1] ^ c[0];

		G[2] = A_in[2] & B_in[2];
		P[2] = A_in[2] ^ B_in[2];
		c[2]= G[2] || (P[2] & c[1]);
		s[2] = P[2] ^ c[1];

		G[3] = A_in[3] & B_in[3]; 
		P[3] = A_in[3] ^ B_in[3]; 
		c[3]= G[3] || (P[3] & c[2]);
		s[3] = P[3] ^ c[2];
	end

assign CO = c[3];
assign S = s;
endmodule