`timescale 1ns/1ns

module sale(
   input                clk   ,
   input                rst_n ,
   input                sel   ,//sel=0,5$dranks,sel=1,10&=$drinks
   input          [1:0] din   ,//din=1,input 5$,din=2,input 10$
 
   output   reg [1:0] drinks_out,//drinks_out=1,output 5$ drinks,drinks_out=2,output 10$ drinks
   output   reg      change_out   
);
    localparam IDLE = 3'd0;
    localparam A1 = 3'd1;
    localparam A2 = 3'd2;

    localparam B1 = 3'd3;
    localparam B2 = 3'd4;
    localparam B3 = 3'd5;

    reg [2:0] state, nxt_state;
    wire [2:0] change = {sel,din};
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            state <= IDLE;
        else
            state <= nxt_state;
    end
    
    always@(*)begin
        case(state)
            IDLE: begin
                case(change)
                    3'b101:nxt_state <= B1;
                    3'b110:nxt_state <= B2;
                    3'b100:nxt_state <= IDLE;

                    3'b000:nxt_state <= IDLE;
                    3'b001:nxt_state <= A1;
                    3'b010:nxt_state <= A2;
                    default:nxt_state <=IDLE;
                endcase
            end

            B1:begin
                case(change)
                    3'b100:nxt_state <= B1;
                    3'b101:nxt_state <= B2;
                    3'b110:nxt_state <= B3;
                endcase
            end

            B2:begin
                 case(change)
                    3'b101:nxt_state <= B1;
                    3'b110:nxt_state <= B2;
                    default:nxt_state <= IDLE;
                endcase
            end 
            B3: begin
               case(change)
                    3'b101:nxt_state <= B1;
                    3'b110:nxt_state <= B2;
                    default:nxt_state <= IDLE;
                endcase
            end 
            A1: begin
                 case(change)
                    3'b001:nxt_state <= A1;
                    3'b010:nxt_state <= A2;
                    default:nxt_state <= IDLE;
                endcase
            end 
            A2:begin
               case(change)
                    3'b001:nxt_state <= A1;
                    3'b010:nxt_state <= A2;
                    default:nxt_state <= IDLE;
               endcase
            end
        endcase
    end

    always@(*)begin
        if(state == B3 ||state == B2)
            drinks_out <=  2'b10;
        else if(state == A1 || state == A2)
            drinks_out <= 2'b01;
        else 
            drinks_out <= 0;
    end

    always@(*)begin
        if(state == B3 || state == A2)
            change_out<=1;
        else 
            change_out <= 0;
    end
   
    
            
endmodule

把两端状态机分开不香吗哈哈