题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
    input clk,
    input rst_n,
    output reg data
    );
    reg [2:0]cnt;
    wire [5:0]data_in;
    assign data_in = 6'b00_1011;
    always @ (posedge clk or negedge rst_n) begin
        if (!rst_n)
            cnt<=0;
        else
            cnt<=(cnt==5)?0:cnt+1;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if (!rst_n)
            data<=0;
        else
            data<=data_in[5-cnt];
    end
endmodule