题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
    input clk,
    input rst_n,
    
    input write_en,
    input [7:0]write_addr,
    input [3:0]write_data,
    
    input read_en,
    input [7:0]read_addr,
    output reg [3:0]read_data
);
    reg [3:0] ram [255:0];
    integer i;
    always@(posedge clk or negedge rst_n)begin
        if(~rst_n) begin
            read_data<=4'b0;
            for(i=0;i<255;i=i+1)
                ram[i] <= 4'b0;
        end
        else if (read_en) 
            read_data<=ram[read_addr];
        else if (write_en) 
            ram[write_addr]<=write_data;
    end
endmodule