题解 | #简易秒表#

`timescale 1ns/1ns

module count_module(
    input clk,
    input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
    );
    always @ (posedge clk or negedge rst_n)begin
        if (~rst_n) begin
            second<=6'd0;
            minute<=6'd0;
        end
        else begin
            second<=(second==6'd60)?6'd1:second+6'd1;
            minute<=(second==6'd60)?minute+1:minute;
        end
    end
            
    
    
endmodule