题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    
    reg [5:0] r_data;
    reg [2:0] cnt;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            cnt <= 3'd0;
        else if (cnt==3'd5)
            cnt <= 3'd0;
        else 
            cnt <= cnt + 1'b1;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            r_data <= 6'b0;
        else if(cnt==3'd0)
            r_data <= {5'b0,data};
        else 
            r_data <= {r_data[4:0],data};
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            match <= 1'b0;
            not_match <= 1'b0;
        end
        else if(cnt==3'd5) begin
            if ({r_data[4:0],data}==6'b0111_00) begin
                match <= 1'b1;
                not_match <= 1'b0;
            end
            else begin
                match <= 1'b0;
                not_match <= 1'b1;
            end
        end
        else begin
            match <= 1'b0;
            not_match <= 1'b0;
        end
    end
    
endmodule