题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit( input A , input clk , input rst_n,

  output   reg        Y   

); reg [1:0] c_state,n_state;

always @ (posedge clk or negedge rst_n)
    if (!rst_n)
         c_state <= 2'b00;
    else 
         c_state <= n_state;


always @ (*)
   if (!rst_n)
         n_state = 2'b00;
   else 
     begin
     case(c_state)
        2'b00:
            if(A == 0)
               n_state = 2'b01;
            else
               n_state = 2'b11;
        2'b01:
            if(A == 0)
               n_state = 2'b10;
            else
               n_state = 2'b00;
        2'b10:
            if(A == 0)
               n_state = 2'b11;
            else
               n_state = 2'b01;
        2'b11:
            if(A == 0)
               n_state = 2'b00;
            else
               n_state = 2'b10;
        
    endcase
   end

 always @ (*)
     if (!rst_n)
          Y = 0;
else if ((n_state == 2'b00) && (A == 0))
         Y = 1;
else if ((n_state == 2'b10)&&(A == 1))
         Y = 1;
else
         Y = 0;

endmodule

三段式状态机最后判断输出时，用当前状态还是下一状态很重要；