`timescale 1ns/1ns module s_to_p( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , output reg valid_b , output reg [5:0] data_b ); //需要一个计数器和寄存器 reg [2:0] data_cnt; reg [5:0] data_reg; always@(posedge clk or negedge rst_n) begin if(!rst_n) ready_a <= 1'b0; else ready_...