`timescale 1ns/1ns module lca_4( input [3:0] A_in , input [3:0] B_in , input C_1 , output wire CO , output wire [3:0] S ); and (g0, A_in[0], B_in[0]); and (g1, A_in[1], B_in[1]); and (g2, A_in[2], B_in[2]); and (g3, A_in[3], B_in[3]); xor (p0, A_in[0], B_in[0]); xor (p1, A_in[1], B_in[1]); xor (p2, ...