`timescale 1ns/1ns module pulse_detect( input clk_fast , input clk_slow , input rst_n , input data_in , output dataout ); reg pulse_a; reg pulse_b1; reg pulse_b2; reg dataout_temp; always@(posedge clk_fast or negedge rst_n)begin if(!rst_n)begin pulse_a<=1'b0; end else if(data_in==1) pulse_a<=~...