`timescale 1ns/1ns module huawei6( input wire clk0 , input wire clk1 , input wire rst , input wire sel , output reg clk_out ); //*************code***********// wire a1o, a2o, en0b, en1b, a3o, a4o; reg en1, en0; assign a1o = sel & en0b; assign a2o = (~sel) & en1b; assign en0b = ~en0;...