`timescale 1ns/1ns module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg valid_out , output reg [127:0] data_out ); reg [4-1 :0] cnt ; reg [120-1:0] data_out_tmp; always@(posedge clk, negedge rst_n) begin if(rst_n == 1'b0 || cnt == 15) cnt <= 0; else i...