`timescale 1ns/1ns module data_cal( input clk, input rst, input [15:0]d, input [1:0]sel, output [4:0]out, output validout ); //*************code***********// reg [4:0] out_reg; reg validout_reg; reg [15:0] d_latch; always @(*) begin case (sel) 0: begin out_reg = 5'd0; validout_reg = 1'b0; d_latch = ...
