`timescale 1ns/1ns module odd_sel( input [31:0] bus, input sel, output check ); //*************code***********// //sel是判断bus中1的个数为奇为偶,1输出奇校验,0输出偶校验 //1的个数为奇,sel为1,则check为1,奇校验成功 //1的个数为奇,sel为0,则check为0,偶校验失败 //1的个数为偶,sel为1,则check为0,奇校验失败 //1的个数为偶,sel为0,则check为1,偶校验成功 wire temp; assign temp=^bus[31:0...