编写一个4bit乘法器模块，并例化该乘法器求解c=12*a+5*b，其中输入信号a,b为4bit无符号数，c为输出。注意请不要直接使用*符号实现乘法功能。
模块的信号接口图如下：
要求使用Verilog HDL语言实现以上功能，并编写testbench验证模块的功能。
[编程题]编写乘法器求解算法表达式
`timescale 1ns/1ns
//12 1100,5 0101
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output[8:0] c
);
wire [7:0]c4;
wire [7:0]c5;
reg [8:0] c_reg;
mul u1(
.clk(clk),
.rst_n(rst_n),
.a(a),
.b(4'd12),
.c(c4)
);
mul u2(
.clk(clk),
.rst_n(rst_n),
.a(b),
.b(4'd5),
.c(c5)
);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)
c_reg<=9'b0;
else
c_reg<=c4+c5;
end
assign c=c_reg;
endmodule
module mul(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output reg [7:0] c
);
wire [7:0] c0,c1,c2,c3;
assign c0={b[0]?a:8'b0};
assign c1={b[1]?{a,1'b0}:8'b0};
assign c2={b[2]?{a,2'b0}:8'b0};
assign c3={b[3]?{a,3'b0}:8'b0};
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)
c<=8'b0;
else
c<=c1+c2+c3+c0;
end
endmodule
//12 1100,5 0101
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output[8:0] c
);
wire [7:0]c4;
wire [7:0]c5;
reg [8:0] c_reg;
mul u1(
.clk(clk),
.rst_n(rst_n),
.a(a),
.b(4'd12),
.c(c4)
);
mul u2(
.clk(clk),
.rst_n(rst_n),
.a(b),
.b(4'd5),
.c(c5)
);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)
c_reg<=9'b0;
else
c_reg<=c4+c5;
end
assign c=c_reg;
endmodule
module mul(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output reg [7:0] c
);
wire [7:0] c0,c1,c2,c3;
assign c0={b[0]?a:8'b0};
assign c1={b[1]?{a,1'b0}:8'b0};
assign c2={b[2]?{a,2'b0}:8'b0};
assign c3={b[3]?{a,3'b0}:8'b0};
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)
c<=8'b0;
else
c<=c1+c2+c3+c0;
end
endmodule
发表于 2022-06-10 11:19:29
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`timescale 1ns/1ns
module calculation(
input clk ,
input rst_n ,
input [3:0] a ,
input [3:0] b ,
output [8:0] c
);
/********************** 参数 **************************/
parameter NUMBER0 = 4'b1100 ;
parameter NUMBER1 = 4'b0101 ;
/********************** 寄存器 **************************/
reg [7:0] r_a_mul_num0 ;
reg [7:0] r_b_mul_num1 ;
reg [8:0] r_c ;
/********************** 组合逻辑 **************************/
assign c = r_c ;
/********************** 时序逻辑 **************************/
// 二级流水
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
r_a_mul_num0 <= 8'd0;
r_b_mul_num1 <= 8'd0;
r_c <= 9'd0;
end
else begin
r_a_mul_num0 <= (a<<3) + (a<<2);
r_b_mul_num1 <= (b<<2) + (b<<0);
r_c <= r_a_mul_num0 + r_b_mul_num1;
end
end
endmodule
发表于 2023-06-17 21:45:47
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`timescale 1ns/1ns module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); reg [7 : 0] r_a_result ; reg [7 : 0] r_b_result ; reg [3 : 0] r_a ; reg [3 : 0] r_b ; assign c = r_a_result + r_b_result; always @(posedge clk&nbs***bsp;negedge rst_n) begin if(!rst_n)begin r_a <= 'd0; r_b <= 'd0; end else begin r_a <= a; r_b <= b; end end always @(posedge clk&nbs***bsp;negedge rst_n) begin if(!rst_n) r_a_result <= 'd0; else r_a_result <= (r_a << 2) + (r_a << 3); end always @(posedge clk&nbs***bsp;negedge rst_n) begin if(!rst_n) r_b_result <= 'd0; else r_b_result <= r_b + (r_b << 2); end endmodule
发表于 2025-03-14 10:52:35
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`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
wire [8:0] c_0, c_1;
multi u_multi_0(
.clk (clk),
.rst_n (rst_n),
.a (a),
.b (4'd12),
.c (c_0)
);
multi u_multi_1(
.clk (clk),
.rst_n (rst_n),
.a (b),
.b (4'd5),
.c (c_1)
);
assign c = c_0 + c_1;
endmodule
module multi(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output reg [8:0] c
);
reg [8:0] c_temp [3:0];
integer i;
always @(posedge clk, negedge rst_n)
if(!rst_n)
begin
for(i=0;i<4;i=i+1)
c_temp[i] <= 0;
end
else
begin
for(i=0;i<4;i=i+1)
c_temp[i] <= b[i] ? a << i : 0;
end
always @(posedge clk, negedge rst_n)
if(!rst_n)
c <= 0;
else
c = c_temp[0] + c_temp[1] + c_temp[2] + c_temp[3];
endmodule
发表于 2025-03-10 03:04:25
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`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
wire [7:0] product_a,product_b;
reg [8:0] c_reg;
multiply multiply_inst_a(
.clk ( clk ),
.rst_n ( rst_n ),
.factor ( a ),
.times ( 4'd12 ),
.product ( product_a )
);
multiply multiply_inst_b(
. clk ( clk ),
. rst_n ( rst_n ),
.factor ( b ),
.times ( 4'd5 ),
.product ( product_b )
);
always@(posedge clk,negedge rst_n) begin
if(!rst_n)
c_reg <= 9'b0;
else
c_reg <= product_a + product_b;
end
assign c = c_reg;
endmodule
module multiply(
input clk,
input rst_n,
input [3:0] factor , //
input [3:0] times ,
output reg [7:0] product
//output [7:0] product
);
wire [7:0] product_0 ;
wire [7:0] product_1 ;
wire [7:0] product_2 ;
wire [7:0] product_3 ;
assign product_0 = ( times[0] == 'b1 )? factor : 'b0;
assign product_1 = ( times[1] == 'b1 )? factor << 'd1 : 'b0;
assign product_2 = ( times[2] == 'b1 )? factor << 'd2 : 'b0;
assign product_3 = ( times[3] == 'b1 )? factor << 'd3 : 'b0;
//assign product = product_0 + product_1 + product_2 + product_3;
always@(posedge clk,negedge rst_n) begin
if(!rst_n)
product <= 8'b0;
else
product <= product_0 + product_1 + product_2 + product_3;
end
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
wire [7:0] product_a,product_b;
reg [8:0] c_reg;
multiply multiply_inst_a(
.clk ( clk ),
.rst_n ( rst_n ),
.factor ( a ),
.times ( 4'd12 ),
.product ( product_a )
);
multiply multiply_inst_b(
. clk ( clk ),
. rst_n ( rst_n ),
.factor ( b ),
.times ( 4'd5 ),
.product ( product_b )
);
always@(posedge clk,negedge rst_n) begin
if(!rst_n)
c_reg <= 9'b0;
else
c_reg <= product_a + product_b;
end
assign c = c_reg;
endmodule
module multiply(
input clk,
input rst_n,
input [3:0] factor , //
input [3:0] times ,
output reg [7:0] product
//output [7:0] product
);
wire [7:0] product_0 ;
wire [7:0] product_1 ;
wire [7:0] product_2 ;
wire [7:0] product_3 ;
assign product_0 = ( times[0] == 'b1 )? factor : 'b0;
assign product_1 = ( times[1] == 'b1 )? factor << 'd1 : 'b0;
assign product_2 = ( times[2] == 'b1 )? factor << 'd2 : 'b0;
assign product_3 = ( times[3] == 'b1 )? factor << 'd3 : 'b0;
//assign product = product_0 + product_1 + product_2 + product_3;
always@(posedge clk,negedge rst_n) begin
if(!rst_n)
product <= 8'b0;
else
product <= product_0 + product_1 + product_2 + product_3;
end
endmodule
有没有好心人帮我看看这个答案哪里有问题呀？？
发表于 2025-02-07 17:28:51
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`timescale 1ns/1ns
module calculation
(
input clk ,
input rst_n ,
input [3:0] a ,
input [3:0] b ,
output [8:0] c
);
wire [7:0] sum_1;
wire [7:0] sum_2;
mul_4 mul_4_inst_1(
.clk (clk) ,
.rst_n (rst_n) ,
.data_1 (a) ,
.data_2 (4'd12) ,
.mul (sum_1)
);
mul_4 mul_4_inst_2(
.clk (clk) ,
.rst_n (rst_n) ,
.data_1 (b) ,
.data_2 (4'd5) ,
.mul (sum_2)
);
assign c = sum_1 + sum_2;
endmodule
module mul_4(
input clk ,
input rst_n ,
input [3:0] data_1 ,
input [3:0] data_2 ,
output reg [7:0] mul
);
reg [7:0] sum [3:0] ;
always @(posedge clk&nbs***bsp;negedge rst_n)
if(!rst_n)
sum[3] <= 0;
else if(data_2[3])
sum[3] <= {data_1,3'b0};
else
sum[3] <= 8'd0;
always @(posedge clk&nbs***bsp;negedge rst_n)
if(!rst_n)
sum[2] <= 0;
else if(data_2[2])
sum[2] <= {data_1,2'b0};
else
sum[2] <= 8'd0;
always @(posedge clk&nbs***bsp;negedge rst_n)
if(!rst_n)
sum[1] <= 0;
else if(data_2[1])
sum[1] <= {data_1,1'b0};
else
sum[1] <= 8'd0;
always @(posedge clk&nbs***bsp;negedge rst_n)
if(!rst_n)
sum[0] <= 0;
else if(data_2[0])
sum[0] <= data_1;
else
sum[0] <= 8'd0;
always @(posedge clk&nbs***bsp;negedge rst_n)
if(!rst_n)
mul <= 0;
else
mul <= sum[3] + sum[2] + sum[1] + sum[0];
endmodule
发表于 2024-08-13 11:44:44
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常数乘变量可转化为移位运算和加减运算的组合。
注意：移位操作符的优先级低于加减操作符，所以移位运算要加括号。
module calculation
(
input wire clk ,
input wire rst_n ,
input wire [3:0] a ,
input wire [3:0] b ,
output reg [8:0] c
);
reg [8:0] a_12 ;
reg [8:0] b_5 ;
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) begin
a_12 <= 9'd0;
b_5 <= 9'd0;
end
else begin
a_12 <= (a <<4) - (a<<2);
b_5 <= (b <<2) + b;
end
end
always@(posedge clk, negedge rst_n)
begin
if(!rst_n)
c <= 9'd0;
else
c <= a_12 + b_5;
end
endmodule
发表于 2024-06-16 11:20:54
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`timescale 1ns/1ns module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); reg [8:0] a_reg_shift8; reg [8:0] a_reg_shift4; reg [8:0] b_reg_shift4; reg [8:0] b_reg_shift1; reg [8:0] a_reg; reg [8:0] b_reg; //一级流水线 always @(posedge clk&nbs***bsp;negedge rst_n) begin if (!rst_n) begin a_reg_shift8 <= 0; a_reg_shift4 <= 0; b_reg_shift4 <= 0; b_reg_shift1 <= 0; end else begin a_reg_shift8 <= a << 3; a_reg_shift4 <= a << 2; b_reg_shift4 <= b << 2; b_reg_shift1 <= b; end end //二级流水线 always @(posedge clk&nbs***bsp;negedge rst_n) begin if (!rst_n) begin a_reg <= 0; b_reg <= 0; end else begin a_reg <= a_reg_shift8 + a_reg_shift4; b_reg <= b_reg_shift4 + b_reg_shift1; end end assign c = a_reg + b_reg; endmodule
发表于 2024-06-14 15:04:34
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`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
reg [8:0] c_reg;
reg [3+3:0] a_left_shift3;
reg [3+2:0] a_left_shift2;
reg [12:0] a_reg;
reg [3:0] b_left_shift0;
reg [3+2:0] b_left_shift2;
reg [9:0] b_reg;
always@(posedge clk or negedge rst_n)begin
if (!rst_n) begin
a_reg <= 13'd0;
// a_left_shift2 <= 6'd0;
// a_left_shift3 <= 7'd0;
end
else begin
// a_left_shift2 <= a << 2; //4*a
// a_left_shift3 <= a << 3; //8*a
// a_reg <= a_left_shift2 + a_left_shift3;
a_reg <= (a << 2) + (a << 3) ;
end
end
always@(posedge clk or negedge rst_n)begin
if (!rst_n) begin
b_reg <= 10'd0;
// b_left_shift0 <= 4'd0;
// b_left_shift2 <= 6'd0;
end
else begin
// b_left_shift2 <= b << 2; //4*b
// b_left_shift0 <= b ;
// b_reg <= b_left_shift2 + b_left_shift0;
b_reg <= (b << 2) + b ;
end
end
always@(posedge clk or negedge rst_n)begin
if (!rst_n)
c_reg <= 9'd0 ;
else begin
c_reg <= a_reg + b_reg ;
end
end
assign c = c_reg[8:0];
endmodule
编辑于 2024-03-13 02:03:20
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`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output reg [8:0] c
);
wire [8:0] c1,c2;
bit_4 b1(
.clk(clk),
.rst_n(rst_n),
.a(a),
.b(4'd12),
.c(c1)
)
;
bit_4 b2(
.clk(clk),
.rst_n(rst_n),
.a(b),
.b(4'd5),
.c(c2)
)
;
always@(posedge clk&nbs***bsp;negedge rst_n)
if(~rst_n)
c<=0;
else
c<=c1+c2;
endmodule
module bit_4(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output reg [8:0] c
);
wire [8:0] co[3:0];
assign co[0]=b[0]?a:0;
assign co[1]=b[1]?{4'b0,a,1'b0}:0;
assign co[2]=b[2]?{3'b0,a,2'b0}:0;
assign co[3]=b[3]?{2'b0,a,3'b0}:0;
//assign c=co[0]+co[1]+co[2]+co[3];
always@(posedge clk&nbs***bsp;negedge rst_n)
if(~rst_n)
c<=0;
else
c<=co[0]+co[1]+co[2]+co[3];
endmodule
发表于 2023-04-11 09:07:28
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`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
wire[8:0] d;
wire[8:0] f;
wire[8:0] e;
reg[8:0] h;
reg[8:0] n;
assign d={1'b0,1'b0,a,1'b0,1'b0,1'b0};
assign e={1'b0,1'b0,1'b0,a,1'b0,1'b0};
assign f={1'b0,1'b0,1'b0,b,1'b0,1'b0};
assign c=n;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
h<='d0;
else
h<=d+e+f+b;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
n<='d0;
else
n<=h;
end
endmodule
发表于 2023-03-06 21:42:47
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`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
wire [8:0]c_r;
reg [8:0]c_r1;
reg [8:0]c_r2;
assign c_r = (a << 4) - (a << 2) + (b << 2) + b;//16a-4a+4b+b
assign c = c_r2;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
c_r1 <= 1'b0;
c_r2 <= 1'b0;
end
else begin
c_r1 <= c_r;
c_r2 <= c_r1;
end
end
endmodule
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
wire [8:0]c_r;
reg [8:0]c_r1;
reg [8:0]c_r2;
assign c_r = (a << 4) - (a << 2) + (b << 2) + b;//16a-4a+4b+b
assign c = c_r2;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
c_r1 <= 1'b0;
c_r2 <= 1'b0;
end
else begin
c_r1 <= c_r;
c_r2 <= c_r1;
end
end
endmodule
发表于 2022-08-04 17:21:01
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