module div2( output reg q, input d,rst ); always @(posedge d) begin if(!rst) q<=0; else q<=~q; end endmodule
module div2 ( input wire clk, input wire rst_n, output reg clk_out ); always @(posedge clk&nbs***bsp;negedge rst_n) begin : proc_ if(~rst_n) begin clk_out <= 0; end else begin clk_out <= ~clk_out; end end endmodule
module div2( input clk , input rst_n , output reg dout ); always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout <= 0; end else begin dout <= !dout; end end endmodule
endmodule
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