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用D触发器实现2倍分频的Verilog描述?

[问答题]
D触发器实现2倍分频的Verilog描述?

答题说明:该题为手动判卷,答案只要写对即可,不用严格满足字符比对。
module div2(
  input  clk,
 input rst,
 out  reg Q
 
)
always@(posedge clk or negedge rst)begin
   if(!rst)
     Q <= 1'b0;
   else 
    Q <= ~Q;
end
endmoudle
发表于 2020-07-29 20:44:31 回复(0)
module div_2(clk,rst_n,clk_2);
input clk;
input rst_n;
output clk_2;
reg clk_2;
always@(posedge clk or negedge rst_n)begin
     if(!rsst_n)
         clk_2<=0;
  else 
       clk_2<=~clk_2;
end
endmodule 
发表于 2019-08-25 13:08:54 回复(0)
module clk_2div(
            Clk,
            Rest_n,
            
            Clk_out
    );
    
    input Clk;
    input Rest_n;
    
    output Clk_out;
    
    reg out;
    
    wire in;
    
    always@(posedge Clk or negedge Rest_n)
        if(!Rest_n)
            out <= 1'd0;
        else
            out <= in;
    
    assign in = ~out;
    assign Clk_out = out;
    
endmodule
发表于 2019-08-28 14:47:58 回复(0)
module div2( output reg q,
             input  d,rst 
           );
always @(posedge d)
begin
   if(!rst)
   q<=0;
   else q<=~q;
end

endmodule

发表于 2019-12-20 11:23:22 回复(0)
always @(posedge clk)
    if (!rst_n) q <= 1'b0;
    else        q <= ~q;
发表于 2022-07-21 10:21:14 回复(0)
module  div_2(
    input wire clk ,
    input wire rst_n,
    ouput  wire div_clk 
);
wire   clk_in;
reg clk_out ;
always@(posedge clk or negedge rst_n)
 if(!rst_n )
     clk_out <= 0;
else 
    clk_out <= in;

assign in = ~clk_out ;
assign div_clk = clk_out;


endmodule 
发表于 2022-03-08 08:42:33 回复(0)
module div2 (
	input wire clk,
	input wire rst_n,
	output reg clk_out
);
	always @(posedge clk&nbs***bsp;negedge rst_n) begin : proc_
		if(~rst_n) begin
			clk_out <= 0;
		end else begin
			clk_out <= ~clk_out;
		end
	end

endmodule

发表于 2021-03-13 20:56:14 回复(0)
module div2_D(
    input wire clk,
    output reg Q)
    always@(posedge clk)
        Q <= ~Q;

endmodule
发表于 2020-02-18 23:47:52 回复(0)
module div2(
input clk_origin,
input rst_n,
output reg clk
)


always@(posedge clk_origin or negedge rst_n)
begin
if(!rst_n)
clk<=1'b0;
else
clk<=~clk;
end

endmodule
发表于 2019-08-18 13:10:41 回复(0)
module div2(
    input      clk    ,
    input      rst_n  ,
    output reg dout
    );

    always  @(posedge clk or negedge rst_n)begin
        if(rst_n==1'b0)begin
            dout <= 0;
        end
        else begin
            dout <= !dout;
        end
    end
endmodule
发表于 2019-04-05 22:20:58 回复(0)
moudule div2(
    input clk,
    input rst_n,
    output clk_div2    
);

reg clk_div2_reg;

always @ (posedge clk or negadge rst_n)
begin
    if(rst_n)
    begin
        clk_div2_reg <= 0;
    emd
    else
    begin
        clk_div2_reg <= ~clk_div2_reg;
    end
end

assign clk_div2 = clk_div2_reg;

endmodule

发表于 2018-09-01 15:48:44 回复(0)