`timescale 1ns/1ns module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 , output reg out1, output reg [1:0]out2 ); //**code// reg [2:0] cnt1; reg [1:0] cnt2; reg cnt3; always@(posedge clk or negedge rst) begin if(!rst) begin ...