`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); parameter A=4'd0,b=4'd1,c=4'd2,d=4'd3,e=4'd4,f=4'd5,g=4'd6,h=4'd7,i=4'd8; reg [3:0]state,next; always@(posedge clk,negedge rst_n) begin if(!rst_n) state<=A; else state<=next;...