题解 | 数据累加输出

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg [2:0] cnt;
//准备好接收上游数据  数据没有发送出去则没有准备好接收
assign ready_a = (valid_b&(~ready_b))? 1'b0:1'b1;

//计数接受的数据 注意：只有valid_a && ready_a同时准备好才能接收数据
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt <= 'd0;
	end
	else if(cnt=='d3 && valid_a && ready_a) begin
		cnt <= 'd0;
	end
	else if(valid_a&&ready_a)begin
		cnt <= cnt + 1;
	end
end

//接收数据累加
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_out <= 'd0;
	end
	else if(cnt=='d0 && ready_a && valid_a)begin
		data_out <= data_in;
	end
	else if(ready_a && valid_a)begin
		data_out <= data_out + data_in;
	end
	
end

//数据有效
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_b <= 1'b0;
	end
	else if((cnt == 'd3) && ready_a && valid_a)begin
		valid_b <= 1'b1;
	end
	else if(ready_b)begin
		valid_b <= 1'b0;
	end
end

endmodule