题解 | 时钟分频（偶数）

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    reg clk_out2,
    output    reg clk_out4,
    output    reg clk_out8
    );
//2分频
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out2 <= 1'b0;
    end
    else begin
        clk_out2 <= ~clk_out2;
    end
end
//4分频
always@(posedge clk_out2 or negedge rst)begin
    if(!rst)begin
        clk_out4 <= 1'b0;
    end
    else begin
        clk_out4 <= ~clk_out4;
    end
end
//8分频
always@(posedge clk_out4 or negedge rst)begin
    if(!rst)begin
        clk_out8 <= 1'b0;
    end
    else begin
        clk_out8 <= ~clk_out8;
    end
end
endmodule