题解 | 输入序列连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

    reg [7:0] reg_a;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            reg_a <= 8'b0; // Reset the register
        end else begin
            reg_a <= {reg_a[6:0], a}; // Shift in the new bit 'a'
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            match <= 1'b0;
        end else if(reg_a == 8'b01110001)begin
            match <= 1'b1; // Match found for the sequence "01110001"
        end else begin
            match <= 1'b0; // No match
        end
    end

endmodule