题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
    reg out2,out4,out8;
    reg [2:0]cnt;
    assign clk_out2=out2;
    assign clk_out4=out4;
    assign clk_out8=out8;
//*************code***********//
always@(posedge clk_in or negedge rst)
if(!rst)begin
    out2<=0;
    out4<=0;
    out8<=0;
    cnt<=0;
end else begin
    out2<=~out2;
    cnt<=cnt+1'b1;

    if(cnt==3'b010|cnt==3'b110)begin
        out4<=~out4;
    end else if(cnt==3'b000|cnt==3'b100)begin
        out4<=~out4;
        out8<=~out8;
    end 
end



//*************code***********//
endmodule