题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  , //本题第一个坑，复位是低电平复位
	input wire [3:0]d ,

	output wire valid_in ,
	output wire dout
);

//*************code***********//
reg [1:0] r_cnt;
reg [3:0] d_reg;

reg valid_reg;
reg dout_reg;

//其次要根据波形图判断数字次序，第一次复位时，没有valid_in生成
always@(posedge clk or negedge rst)begin
  if(!rst)
    r_cnt <= 1'b0;
  else if(r_cnt == 2'b11)
    r_cnt <= 1'b0;
  else
    r_cnt <= r_cnt + 1'b1;
end

//需要寄存d的值，但是又不能只采样d_reg的值作为移位输出
always@(posedge clk or negedge rst)begin
 if(!rst)begin
    d_reg     <= 1'b0;
	valid_reg <= 1'b0;
	dout_reg  <= 1'b0;
 end
 else begin
    case(r_cnt)
      2'b00:begin
    	  d_reg    <= d_reg;
    	  valid_reg <= 1'b0;
    	  dout_reg    <= d_reg[2];
    	end
    	2'b01:begin
    	  d_reg     <= d_reg;
    	  valid_reg <= 1'b0;
    	  dout_reg  <= d_reg[1];
    	end
    	2'b10:begin
    	  d_reg     <= d_reg;
    	  valid_reg <= 1'b0;
    	  dout_reg  <= d_reg[0];
    	end
    	2'b11:begin
    	  d_reg     <= d;
    	  valid_reg <= 1'b1;
    	  dout_reg  <= d[3];
    	end
    	default:begin
    	  d_reg     <= 1'b0;
    	  valid_reg <= 1'b0;
    	  dout_reg  <= 1'b0;
    	end
    endcase
 end
end

assign valid_in = valid_reg;
assign dout = dout_reg;


//*************code***********//

endmodule