题解 | #多功能数据处理器#

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input unsigned[1:0]select,
	output reg signed [8:0]c
);
	always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		c<=0;
	end
	else begin
		case(select)
		2'd0:begin
			c <= a;
		end
		2'd1:begin
			c <= b;
		end
		2'd2:begin
			c <= {1'b0,a}+{1'b0,b};
		end
		2'd3:begin
			c <= {1'b0,a}-{1'b0,b};
		end
		endcase
	end

	end
endmodule