题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0] count1;
reg [23:0] mid_reg1;
reg [23:0] mid_reg2;
reg [23:0] mid_reg3;
reg [23:0] mid_reg4;
reg [23:0] mid_reg5;
reg [23:0] mid_reg6;
reg [23:0] mid_reg7;
reg [23:0] mid_reg8;
reg [23:0] mid_reg9;
reg [23:0] mid_reg10;
reg [23:0] mid_reg11;
reg [23:0] mid_reg12;
reg [23:0] mid_reg13;
reg [23:0] mid_reg14;
reg [23:0] mid_reg15;
reg [23:0] mid_reg16;

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		count1 <= 3'b0;
	end
	else begin
		if(valid_in)begin
			count1 <= count1 + 1;
		end
		else begin
			count1 <= count1;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out <= 1'b0;
	end
	else begin
		if((count1 == 5 || count1 == 10 || count1 == 15) && valid_in)begin
			valid_out <= 1'b1;
		end
		else begin
			valid_out <= 1'b0;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		mid_reg1 <= 24'b0;
		mid_reg2 <= 24'b0;
		mid_reg3 <= 24'b0;
		mid_reg4 <= 24'b0;
		mid_reg5 <= 24'b0;
		mid_reg6 <= 24'b0;
		mid_reg7 <= 24'b0;
		mid_reg8 <= 24'b0;
		mid_reg9 <= 24'b0;
		mid_reg10 <= 24'b0;
		mid_reg11 <= 24'b0;
		mid_reg12 <= 24'b0;
		mid_reg13 <= 24'b0;
		mid_reg14 <= 24'b0;
		mid_reg15 <= 24'b0;
		mid_reg16 <= 24'b0;
	end
	else begin
		if(valid_in)begin
			case(count1)
			4'b0000:mid_reg1 <= data_in;
			4'b0001:mid_reg2 <= data_in;
			4'b0010:mid_reg3 <= data_in;
			4'b0011:mid_reg4 <= data_in;
			4'b0100:mid_reg5 <= data_in;
			4'b0101:mid_reg6 <= data_in;
			4'b0110:mid_reg7 <= data_in;
			4'b0111:mid_reg8 <= data_in;
			4'b1000:mid_reg9 <= data_in;
			4'b1001:mid_reg10 <= data_in;
			4'b1010:mid_reg11 <= data_in;
			4'b1011:mid_reg12 <= data_in;
			4'b1100:mid_reg13 <= data_in;
			4'b1101:mid_reg14 <= data_in;
			4'b1110:mid_reg15 <= data_in;
			4'b1111:mid_reg16 <= data_in;
			endcase
		end
		else begin
			mid_reg1 <= mid_reg1;
			mid_reg2 <= mid_reg2;
			mid_reg3 <= mid_reg3;
			mid_reg4 <= mid_reg4;
			mid_reg5 <= mid_reg5;
			mid_reg6 <= mid_reg6;
			mid_reg7 <= mid_reg7;
			mid_reg8 <= mid_reg8;
			mid_reg9 <= mid_reg9;
			mid_reg10 <= mid_reg10;
			mid_reg11 <= mid_reg11;
			mid_reg12 <= mid_reg12;
			mid_reg13 <= mid_reg13;
			mid_reg14 <= mid_reg14;
			mid_reg15 <= mid_reg15;
			mid_reg16 <= mid_reg16;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_out <= 128'b0;
	end
	else begin
			case(count1)
			4'b0101:begin
				data_out <= {mid_reg1, mid_reg2, mid_reg3, mid_reg4, mid_reg5, data_in[23:16]};
			end
			4'b1010:begin
				data_out <= {mid_reg6[15:0], mid_reg7, mid_reg8, mid_reg9, mid_reg10, data_in[23:8]};
			end
			4'b1111:begin
				data_out <= {mid_reg11[7:0], mid_reg12, mid_reg13, mid_reg14, mid_reg15, data_in};
			end
			default:begin
				data_out <= data_out;
			end
			endcase
		end
end


endmodule