题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg Clk_out2;
reg Clk_out4;
reg Clk_out8;

always@(posedge clk_in or negedge rst)begin
    if(!rst)
        Clk_out2 <= 1'b0;
    else
        Clk_out2 <= ~Clk_out2;
end

always@(posedge Clk_out2 or negedge rst)begin
    if(!rst)
        Clk_out4 <= 1'b0;
    else
        Clk_out4 <= ~Clk_out4;
end

always@(posedge Clk_out4 or negedge rst)begin
    if(!rst)
        Clk_out8 <= 1'b0;
    else
        Clk_out8 <= ~Clk_out8;
end

assign clk_out2 = Clk_out2;
assign clk_out4 = Clk_out4;
assign clk_out8 = Clk_out8;



//*************code***********//
endmodule