题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);


genvar i;
generate
	for(i = 0; i < 4; i = i + 1)begin: ADD
		wire g = A_in[i] & B_in[i];
		wire p = A_in[i] ^ B_in[i];
		wire C;
		if (i == 0)begin
			assign S[i] = p ^ C_1;
			assign C = g + (p & C_1);
		end else begin
			assign S[i] = p ^ ADD[i-1].C;
			assign C = g + (p & ADD[i-1].C);
			if (i == 3)begin
				assign CO = C;
			end
		end
		
	end

endgenerate

endmodule

逻辑运算计算加括号QAQ，测试三遍才发现是assign C = g + (p & C_1);而不是assign C = g + p & C_1;