题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg     T1;

always@(posedge clk or negedge rst)
    if(rst==1'b0)
        T1<=1'b0;
    else if(data==1'b1)
        T1<=~T1;
    else    
        T1<=T1;

always@(posedge clk or negedge rst)
    if(rst==1'b0)
        q<=1'b0;
    else if(T1==1'b1)
        q<=~q;
    else
        q<=q;
//*************code***********//
endmodule