题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//

reg clk1, clk2;
reg [2:0]  cnt;

always @(posedge clk_in or negedge rst) begin
    if (!rst) cnt <= 0;
    else if(cnt == 'd6) cnt <= 0;
    else cnt <= cnt + 1;
end

always @(posedge clk_in or negedge rst) begin
    if (!rst) clk1 <= 0; 
    else if (cnt == 'd3) clk1 = ~clk1;
    else if(cnt == 'd6) clk1 = ~clk1;
    else clk1 <= clk1;
end

always @(negedge clk_in or negedge rst) begin
    if (!rst) clk2 <= 0; 
    else if (cnt == 'd3) clk2 = ~clk2;
    else if(cnt == 'd6) clk2 = ~clk2;
    else clk2 <= clk2;
end

assign clk_out7 = clk1 || clk2;

//*************code***********//
endmodule