题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out,
output reg [1:0]mux
);
//*************code***********//
always@(d0,d1,d2,d3,sel)
	begin
        case(sel)
        	2'b00:mux = d3;
            2'b01:mux = d2;
            2'b10:mux = d1;
            default:mux = d0;
        endcase
    end
assign mux_out = mux;
//*************code***********//
endmodule