题解 | #串行进位加法器#

`timescale 1ns/1ns

module add_4(
   input         [3:0]  A   ,
   input         [3:0]  B   ,
   input                Ci  , 

   output	wire [3:0]  S   ,
   output   wire        Co   
);

    genvar i;
    generate begin: G
        wire [4:0] c;
        assign c[0] = Ci;
        assign Co = c[4];
        for(i=0; i<=3; i=i+1) add_full FA(A[i], B[i], c[i], S[i], c[i+1]);
    end 
    endgenerate

endmodule