题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
    
    wire hS, hC;

    add_half HA(A, B, hS, hC);

    assign S = hS^Ci;
    assign Co = hC | A&Ci | B&Ci; // majority function.  

endmodule