题解 | #占空比50%的奇数分频#
占空比50%的奇数分频
https://www.nowcoder.com/practice/ccfba5e5785f4b3f9d7ac19ab13d6b31
`timescale 1ns/1ns
module odo_div_or
(
input wire rst ,
input wire clk_in,
output wire clk_out7
);
//*************code***********//
/*
reg [2:0] cnt;
always@(posedge clk_in or negedge rst)begin
if(!rst)begin
cnt <= 0;
end
else if(cnt == 3'd6)begin
cnt <= 0;
end
else begin
cnt <= cnt + 1'b1;
end
end
//上升沿产生3个时钟周期的高电平，4个时钟周期低电平
reg clkp_div7_r;
always@(posedge clk_in or negedge rst)begin
if(!rst)begin
clkp_div7_r <= 0;
end
else if(cnt == 2)begin //3,4,5,6=0
clkp_div7_r <= 0;
end
else if(cnt == 6)begin //0,1,2=1
clkp_div7_r <= 1;
end
end
//下降沿产生3个时钟周期的高电平，4个时钟周期低电平
reg clkn_div7_r;
always@(negedge clk_in or negedge rst)begin
if(!rst)begin
clkn_div7_r <= 0;
end
else if(cnt == 2)begin
clkn_div7_r <= 0;
end
else if(cnt == 6)begin
clkn_div7_r <= 1;
end
end
//或操作，往往使用基本逻辑单元库
// or (clk_out7,clkp_div7_r,clkn_div7_r);
assign clk_out7 = (clkp_div7_r | clkn_div7_r);
*/
reg [2:0] cnt;
always@(posedge clk_in or negedge rst)begin
if(!rst)begin
cnt <= 0;
end
else if(cnt == 3'd6)begin
cnt <= 0;
end
else begin
cnt <= cnt + 1'b1;
end
end
//上升沿产生3个时钟周期的高电平，4个时钟周期低电平
reg clkp_div7_r;
always@(posedge clk_in or negedge rst)begin
if(!rst)begin
clkp_div7_r <= 0;
end
else if(cnt == 3)begin //4,5,6=1
clkp_div7_r <= 1;
end
else if(cnt == 6)begin //0,1,2,3=0
clkp_div7_r <= 0;
end
end
//下降沿产生3个时钟周期的高电平，4个时钟周期低电平
reg clkn_div7_r;
always@(negedge clk_in or negedge rst)begin
if(!rst)begin
clkn_div7_r <= 0;
end
else if(cnt == 3)begin
clkn_div7_r <= 1;
end
else if(cnt == 6)begin
clkn_div7_r <= 0;
end
end
//或操作，往往使用基本逻辑单元库
// or (clk_out7,clkp_div7_r,clkn_div7_r);
assign clk_out7 = (clkp_div7_r | clkn_div7_r);
//*************code***********//
endmodule
