题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0] cnt_10;
reg [23:0] men[15:0];




integer i;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt_10 <= 0;
		for(i=0;i<=15;i=i+1)begin
			men[i] <= 0;
		end
	end
	else if(valid_in)begin
		men[cnt_10] <= data_in;
		cnt_10 <= cnt_10 + 1'b1;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out <= 0;
		data_out <= 0;
	end
	if(valid_in)begin
		case(cnt_10)
			4'd5 : begin
				valid_out <= 1;
				// data_out <= {men[0],men[1],men[2],men[3],men[4],men[5][23:16]};
				data_out <= {men[0],men[1],men[2],men[3],men[4],data_in[23:16]};
			end
			4'd10 : begin
				valid_out <= 1;
				// data_out <= {men[5][15:0],men[6],men[7],men[8],men[9],men[10][23:8]};
				data_out <= {men[5][15:0],men[6],men[7],men[8],men[9],data_in[23:8]};
			end
			4'd15 : begin
				valid_out <= 1;
				// data_out <= {men[10][7:0],men[11],men[12],men[13],men[14],men[15]};
				data_out <= {men[10][7:0],men[11],men[12],men[13],men[14],data_in};
			end
			default : begin  valid_out <= 0; end
		endcase
	end
	else begin
		valid_out <= 0;
	end
end
	
	



endmodule