题解 | #五到一选择器#

`timescale 1ns/1ns

module top_module( 
    input [3:0] a, b, c, d, e, 
    input [2:0] sel,
    output reg [3:0] out );

always @( a or b or c or d or e or sel )
begin
    case( sel )
        2'd0: out = a;
        2'd1: out = b;
        2'd2: out = c;
        2'd3: out = d;
        2'd4: out = e;
        default: out = 4'd0;
    endcase
end

endmodule