题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg [2:0]count;
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        count<=0;
    end
    else begin
        if(count==3'd7)begin
            count<=0;
        end
        else begin
            count<=count+1;
        end
    end
end

reg out2_reg;
reg out4_reg;
reg out8_reg;
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        out2_reg<=0;
    end
    else begin
        case(count)
        3'd0:out2_reg<=1;
        3'd2:out2_reg<=1;
        3'd4:out2_reg<=1;
        3'd6:out2_reg<=1;
        default:out2_reg<=0;
        endcase
    end
end
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        out4_reg<=0;
    end
    else begin
        case(count)
        3'd0:out4_reg<=1;
        3'd1:out4_reg<=1;
        3'd4:out4_reg<=1;
        3'd5:out4_reg<=1;
        default:out4_reg<=0;
        endcase
    end
end
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        out8_reg<=0;
    end
    else begin
        if(count<4)begin
            out8_reg<=1;
        end
        else begin
            out8_reg<=0;
        end
    end
end

assign clk_out2=out2_reg;
assign clk_out4=out4_reg;
assign clk_out8=out8_reg;
//*************code***********//
endmodule

写的有点丑，但能运行