题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter IDLE = 5'b00001;
parameter S0   = 5'b00010;
parameter S1   = 5'b00100;
parameter S2   = 5'b01000;
parameter S3   = 5'b10000;

// one step
reg [4:0] cs;
reg [4:0] ns;
always @ (posedge clk or negedge rst) begin
    if(~rst) begin
        cs <= IDLE;
    end 
    else begin
        cs <= ns;
    end 
end 

// two step
always @ (*) begin
    case(cs) 
        IDLE  : ns = (data == 1'b1) ? S0 : IDLE;
        S0    : ns = (data == 1'b0) ? S1 : S0;
        S1    : ns = (data == 1'b1) ? S2 : IDLE;
        S2    : ns = (data == 1'b1) ? S3 : S1;
        S3    : ns = (data == 1'b1) ? S0 : S1;
        default : ns = IDLE;
    endcase
end 

//three step
always @ (posedge clk or negedge rst) begin
    if(~rst) begin
        flag <= 1'b0;
    end 
    else begin
        if(cs == S3) begin
            flag <= 1'b1;
        end 
        else begin
            flag <= 1'b0;
        end 
    end 
end

//*************code***********//
endmodule