题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg a1;
always @ (posedge clk or negedge rst_n)
begin
    if( ~rst_n ) begin
        a1 <= 1'b0;
        rise <= 1'b0;
        down <= 1'b0;
    end 
    else begin
        a1 <= a;
        if(a & ~a1)
            rise <= 1'b1;
			//a是现在这一拍的状态，a1是上一拍的状态
        else 
            rise <= 1'b0;
        if(~a & a1)
            down <= 1'b1;
        else
            down <= 1'b0;
    end 
end 
       
endmodule

这是个比较常用的小模块，也可以不用写得这么麻烦