题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output wire flag
);
reg [4:0] data_m;
always @(posedge clk or negedge rst) begin
    if (!rst) begin
        data_m <= 'b0;
    end
    else if(!flag) begin
        data_m <= {data_m[3:0],data};
    end
    else
        data_m <= 'b0;
end
assign flag = (data_m == 'b10111) ? 1:0;

endmodule