题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg q_tmp;
always@(posedge clk or negedge rst)begin
    if(rst == 1'b0) begin
        q_tmp <= 1'b0;
        q     <= 1'b0;
    end
    else begin
        q_tmp <= data^q_tmp;
        q     <= q_tmp^q;
    end
end

//*************code***********//
endmodule