题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

  reg [3:0] seq;

  always @(posedge clk or negedge rst_n) 
  begin
    if(~rst_n)
        seq <= 4'b0;
    else
        seq <= data_valid? {seq[2:0], data} : seq;
  end

  always @(*) 
  begin
    if(~rst_n)
        match = 1'b0;
    else
        match = (seq==4'b0110 && data_valid);
  end

endmodule