题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
/*三段式*/
parameter idle=0,s0=1,s1=2,s2=3,s3=4;
reg[2:0]cs,ns;
reg flag_reg;
always@(posedge clk or negedge rst)begin
	if(!rst) cs<=idle;
	else     cs<=ns;
end
always@(*)begin
	if(!rst)ns=idle;
	else begin
		case(cs)
		idle:ns=data?s0:idle;
		s0:ns=data?s0:s1;
		s1:ns=data?s2:idle;
		s2:ns=data?s3:s1;
		s3:ns=data?s0:s1;
		default:ns=idle;
		endcase
	end
end
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		flag_reg<=0;
	end
	else begin
		case(ns)
		idle: flag_reg<=0;
		s0:   flag_reg<=0;
		s1:	  flag_reg<=0;
		s2:   flag_reg<=0;
		s3:   flag_reg<=1;
		default:flag_reg<=0;
	endcase
	end
end
always@(posedge clk or negedge rst)begin
	if(!rst) flag<=0;
	else     flag<=flag_reg;
end
//*************code***********//
endmodule