题解 | #多功能数据处理器#

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);

wire signed [8:0]data;
assign data=(select[0] == 0)?((select[1] == 0)? a:(a+b)):((select[1] == 0)?b:(a-b));

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        c<=0;
	end
	else begin
        c<=data;
	end
end




endmodule