题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//重叠就是检测完不会到初始态
//非重叠就是回到初始态！！！
parameter S0 = 0,S1 = 1,S2=2,S3=3,S4=4;
reg [2:0]state ,next_state;
always@(posedge clk or negedge rst)begin
	if(~rst)begin
		state <= 0;
	end
	else begin
		state <= next_state;
	end
end

always@(*)begin
	if(~rst)begin
		next_state <= 0;
	end
	else begin
		case(state)
		S0	:	next_state = data ? S1 : S0 ;
		S1	:	next_state = data ? S1 : S2 ;
		S2	:	next_state = data ? S3 : S0 ;
		S3	:	next_state = data ? S4 : S2 ;
		S4	:	next_state = data ? S1 : S2 ;
		default : next_state = S0 ;
		endcase
	end
end

always@(posedge clk, negedge rst)begin
	if(~rst)begin
		flag <= 0;
	end
	else begin
		flag <= state == 4 ;
	end
end
//*************code***********//
endmodule

重叠就是检测完不会回到初始态，而是在有效状态里面返回；非重叠就是回到初始态重新开始。