题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

reg data_in_reg ;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) 
	    data_in_reg <= 1'b0    ;
    else 
	    data_in_reg <= data_in ; 
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) 
	    data_out <= 1'b0    ;
    else 
	    data_out <= (data_in & (~data_in_reg)) ; 
end
endmodule