题解 | #异步FIFO#

`timescale 1ns/1ns

/***************************************RAM*****************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/***************************************AFIFO*****************************************/
module asyn_fifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					wclk	, 
	input 					rclk	,   
	input 					wrstn	,
	input					rrstn	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output wire				wfull	,
	output wire				rempty	,
	output wire [WIDTH-1:0]	rdata
);

   
localparam		 	ADDR_WIDTH = $clog2(DEPTH);

reg 				[ADDR_WIDTH:0] 					waddr;
reg 				[ADDR_WIDTH:0] 					raddr;

always@(posedge wclk or negedge wrstn)
	if(!wrstn)
		waddr <= 'b0;
	else begin
		waddr <= (winc & !wfull) ? (waddr + 1'b1) : waddr;
	end

always@(posedge rclk or negedge rrstn)
	if(~rrstn)
		raddr <= 'b0;
	else begin
		raddr <= (rinc & !rempty) ? (raddr + 1'b1) : raddr;
	end

wire 			[ADDR_WIDTH:0] 			waddr_gray;
wire 			[ADDR_WIDTH:0]			raddr_gray;

reg 			[ADDR_WIDTH:0] 			waddr_gray_reg;
reg 			[ADDR_WIDTH:0] 			raddr_gray_reg;

assign waddr_gray = waddr ^ (waddr>>1);
assign raddr_gray = raddr ^ (raddr>>1);


always@(posedge wclk or negedge wrstn)
	if(!wrstn)
		waddr_gray_reg <= 'b0;
	else
		waddr_gray_reg <= waddr_gray;

always@(posedge rclk or negedge rrstn)
	if(!rrstn)
		raddr_gray_reg <= 'b0;
	else
		raddr_gray_reg <= raddr_gray;



// raddr 同步到写时钟域
reg 			[ADDR_WIDTH:0] 					w_gray_sync0;
reg 			[ADDR_WIDTH:0] 					w_gray_sync;

always@(posedge wclk or negedge wrstn)begin
	if(!wrstn) begin
		r_gray_sync0	<= 'b0;
		r_gray_sync 	<= 'b0;
	end
	else begin
		r_gray_sync0 	<= raddr_gray_reg;
		r_gray_sync 	<= r_gray_sync0;
	end
end


//waddr 同步到 读时钟域
reg  			[ADDR_WIDTH:0] 					r_gray_sync0;
reg  			[ADDR_WIDTH:0] 					r_gray_sync;

always@(posedge rclk or negedge rrstn)begin
	if(!rrstn)begin
		w_gray_sync0 	<= 'b0; 				
		w_gray_sync 	<= 'b0;
	end 
	else begin
		w_gray_sync0 	<= waddr_gray_reg; 				
		w_gray_sync	 	<= w_gray_sync0;			
	end
end

// 空满信号生成

assign wfull  =(waddr_gray_reg =={~r_gray_sync[ADDR_WIDTH:ADDR_WIDTH-1],r_gray_sync[ADDR_WIDTH-2:0]});
assign rempty =(raddr_gray_reg == w_gray_sync);


dual_port_RAM #( 
	.DEPTH(DEPTH),
	.WIDTH(WIDTH)
)
dual_ram_inst(
	.wclk(wclk),
	.wenc(winc & ~wfull),
	.waddr(waddr[ADDR_WIDTH-1:0]),
	.wdata(wdata),    	
	.rclk(rclk),
	.renc(rinc & ~rempty),
	.raddr(raddr[ADDR_WIDTH-1:0]),  
	.rdata(rdata)
);  
endmodule