题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	
reg 				[3:0] 				mem [7:0];

integer i;

always@(*)
	if(!rst_n)begin
		read_data <= 4'd0;
		for (i = 0; i < (2**3) ;i = i +1 )
			mem[i] <= 4'd0;
	end
	else if(write_en)
		mem[write_addr] <= write_data;
	else
		mem[write_addr] <= 4'd0;



always@(*)
	if(!rst_n)begin
		read_data <= 4'd0;
	end
	else if(read_en)
		read_data <= mem[read_addr];
	else
		read_data <= 4'd0;








endmodule