题解 | #序列发生器#
序列发生器
https://www.nowcoder.com/practice/1fe78a981bd640edb35b91d467341061
`timescale 1ns/1ns
module sequence_generator(
input clk,
input rst_n,
output reg data
);
reg [5:0]dd;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) data<=0;
else data<=dd[5];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) dd<=6'b001011;
else dd<={dd[4:0],dd[5]};
end
endmodule
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