题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0]d_r;
always@(posedge clk or rst)begin
    if(!rst)begin
        out<=0;
        validout<=0;
        d_r<=0;
    end else case(sel)
        2'b00:begin
           d_r<=d; 
           out<=0;
           validout<=0;
        end
        2'b01:begin 
            out<=d_r[3:0]+d_r[7:4];
            validout<=1;
        end
        2'b10:begin 
            out<=d_r[3:0]+d_r[11:8];
            validout<=1;
        end
        2'b11:begin
            out<=d_r[3:0]+d_r[15:12];
            validout<=1;
        end
        default:begin
            out<=0;
            validout<=0;
        end
    endcase
end
//*************code***********//
endmodule