题解 | #五到一选择器#

`timescale 1ns/1ns

module top_module( 
    input [3:0] a, b, c, d, e, 
    input [2:0] sel,
    output reg [3:0] out );
    always@(*)begin
    case(sel)
        3'd0:out=a;
        3'd1:out=b;
        3'd2:out=c;
        3'd3:out=d;
        3'd4:out=e;
    default:out=0;
    endcase
    end 
endmodule